Processor reliability enhancement through compiler-directed register file peak temperature reduction

Abstract—Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliability. Temperature hotspots not only accelerate the physical failure mechanisms such as electromigration and di-electric breakdown, but furthermore make the system more vulnerable to timing-related intermittent failures. Traditional thermal management techniques suffer from considerable per-formance overhead as the entire processor needs to be stalled or slowed down to preclude heat accumulation. Given the significant temporal and spatial variations of the chip-wide temperature, we propose in this paper a technique that directly targets one of the resources that is most likely to overheat in current processors, namely, the register files. Instead of duplicating or physically distributing the register file, we suggest to attain power density control through exploiting the extant spatial slack associated with register file accesses. Based on application-specific access profiles, a compiler-directed register shuffling strategy is proposed to deterministically construct the logical to physical register map-ping in a rotating manner. Simulation results confirm that the proposed technique attains, within a limited hardware budget and negligible performance degradation, effective reduction in peak temperature and hence in the expected fault rates for the entire chip. I

A novel scan architecture for power-efficient, rapid test

Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suffer from prolonged test time and excessive test power due to numerous shift op-erations. The high density of the unspecified bits in test data enables the utilization of the test response data captured in the scan chain for the generation of the subsequent test stimulus, thus reducing both test time and test data volume. The pro-posed scan-based test scheme accesses only a subset of scan cells for loading the subsequent test stimulus while freezing the remaining scan cells with the response data captured, thus decreasing the scan chain transitions during shift operations. The experimental results confirm the significant reductions in test application time, test data volume and test power achieved by the proposed scan-based testing methodology.

Fault dictionary size reduction through test response superposition

Abstract Th

On mismatch in the deep sub-micron era-from physics to circuits

Ahstract-Rapid decrease in feature sizes has increasingly accentuated the importance of matching between transistors. Deep submicron designs will further emphasize the need to focus on the effects of mismatch. Furthermore, increased efforts on high level analog device modeling will necessitate accompanying mismatch simulation and measurement methods. The deep sub-micron era forces circuit designers to learn more about the physim and the technology of transistors, This study intraduces a method and assists circuit designers in including this method in their traditional design flow of circuits. By proposing a solution to the problem of building a modeling bridge between transistor mismatch and circuit response to it, we hope to enable designers to incorporate low level mismatch information in their higher level design

Energy-Ecient Physically Tagged Caches for Embedded Processors with Virtual Memory

ABSTRACT In this paper we present a low-power tag organization for physically tagged caches in embedded processor

Implementing Synthetic Aperture Radar Backprojection in Chisel – A Field Report

Chisel is an emerging hardware description language which is especially popular in the RISC-V community. In this report, we evaluate its application in the field of general digital hardware design. A dedicated hardware implementation of a Synthetic Aperture Radar (SAR) processing algorithm is used as an example case for a real-world application. It is targeting a modern high performance FPGA platform. We analyze the difference in code size compared to a VHDL implementation. In contrast to related publications, we classify the code lines into several categories, providing a more detailed view. Overall, the number of lines was reduced by 74% while the amount of boilerplate code was reduced by 83%. Additionally, we report on our experience using Chisel in this practical application. We found the generative concept and the flexibility introduced by modern software paradigms superior to traditional hardware description languages. This increased productivity, especially during timing closure. However, additional programming skills not associated with classic hardware design are required to fully leverage its advantages. We recommend Chisel as a language for all hardware design tasks and expect its popularity to increase in the future

Kekonvergenan eksp0ektrasi variabel random dalam integral labesgue

Suatu variabel random dapat dinyatakan sebagai jumlahan fungsi sederhana. Selanjutnya ekspektasinya dapat dinyatakan dalam ekspektasi Integral Lebesgue sebagai limit ekspektasi barisan variabel random .Untuk mutlak dari yang lebih besar atau sama dengan n juga konvergen ke & maka ekspektasi dari mutlak berhingga, ekspektasi tn konvergen ke ekspektasi dan konvergensi tn terhadap dalam ekspektasi konvergen ke nol. This document is Undip. Institutional Repository Collection. The author(s) or copyright owner(s) agree that UNDIP-IR may, without changing the content, translate the submission to any medium or format for the purpose of preservation. The author(s) or copyright owner(s) also agree that UNDIP-IR may keep more than one copy of this submission for purpose of security, back-up and preservation: http://eprints.undipiSLid